1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a semiconductor package structure with reduced parasite capacitance and method of fabricating the same, which is designed for the fabrication of a flip-chip (FC) type of semiconductor package, and which features the reduction of parasite capacitance in the package structure for ensured electrical performance during actual operation of the packaged integrated circuitry, and also allows the overall package body to be made more compact in size.
2. Description of Related Art
FC (Flip-Chip) is a more advanced type of semiconductor packaging technology which is characterized by that the semiconductor chip is mounted in an upside-down (i.e., flip chip) manner over the substrate and bonded to the same by means of solder bumps. Further, the flip chip is electrically connected to solder balls (i.e., ball grid array, BGA) implanted on the back side of the substrate for electrical connections to a printed circuit board (PCB). Since flip-chip package can be fabricated without the use of bonding wires, it allows the overall package body to be made more compact in size.
FIG. 1 is a schematic diagram showing a sectional view of a conventional flip-chip package structure. As shown, the flip-chip package structure includes a substrate 10, a passive component 20, and a semiconductor chip 30; wherein the substrate 10 has a front surface 10a and a back surface 10b, and whose front surface 10a is formed with a plurality of pads, including at least a pair of passive-component pads 11, 12 and a group of signal pads 13, where the passive-component pads 11, 12 are used for ground/power connections with the passive component 20 and the signal pads 13 are used for signal connections. Moreover, these pads 11, 12, 13 extend from the front surface 10a to the back surface 10b of the substrate 10 through electrically-conductive vias ((not shown) for electrical connection to solder balls 15 on the back surface 10b of the substrate 10. The passive component 20 can be either a resistor or a capacitor, and which has two connecting ends: a first connecting end 21 and a second connecting end 22 respectively bonded to the passive-component pads 11, 12. The chip 30 has an active surface 30a and an inactive surface 30b, where the active surface 30a is defined with a plurality of ground/power pads 31, 32 and a plurality of signal pads 33. Moreover, the chip 130 is formed with a plurality of solder bumps 40 for electrically connecting the signal pads 33 and the ground/power pads 31, 32 to corresponding pads 13 on the front surface 10a of the substrate 10 to form a flip-chip package structure. In this flip-chip package structure, the electrical connections with external circuitry are conducted through the vias for signal transmission, grounding, and power supply, and the passive component 20 is electrically connected to the chip 30 by connecting the ground/power pads 31, 32 by way of vias (not shown) or electrically-conductive traces 14 to the passive-component pads 11, 12.
One drawback to the forgoing package structure, however, is that the long length of traces 14 that are interconnected between the passive component 20 and the chip 30 would easily cause parasite capacitance that would adversely degrade the electrical performance of the packaged chip 30 during high-frequency operation. Moreover, since the passive component 20 is mounted outside the die-mounting area on the substrate 10, it requires the use of a large-area substrate for the mounting of the passive component 20 and the chip 30, undesirably making the overall package body unsatisfactorily large.